Sanu Mathew, Sudhir Satpathy, Vikram Suresh, Mark Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Greg Chen, Ram Krishnamurthy, Vivek De. A 4fJ/bit delay-hardened physically unclonable function circuit with selective bit destabilization in 14nm tri-gate CMOS. In 2016 IEEE Symposium on VLSI Circuits, VLSIC 2016, Honolulu, HI, USA, June 15-17, 2016. pages 1-2, IEEE, 2016. [doi]
@inproceedings{MathewSSAKAHCKD16,
title = {A 4fJ/bit delay-hardened physically unclonable function circuit with selective bit destabilization in 14nm tri-gate CMOS},
author = {Sanu Mathew and Sudhir Satpathy and Vikram Suresh and Mark Anders and Himanshu Kaul and Amit Agarwal and Steven Hsu and Greg Chen and Ram Krishnamurthy and Vivek De},
year = {2016},
doi = {10.1109/VLSIC.2016.7573554},
url = {http://dx.doi.org/10.1109/VLSIC.2016.7573554},
researchr = {https://researchr.org/publication/MathewSSAKAHCKD16},
cites = {0},
citedby = {0},
pages = {1-2},
booktitle = {2016 IEEE Symposium on VLSI Circuits, VLSIC 2016, Honolulu, HI, USA, June 15-17, 2016},
publisher = {IEEE},
isbn = {978-1-5090-0635-9},
}