The following publications are possibly variants of this publication:
- SAR+ΔΣ ADCs with open-loop integrator using dynamic amplifierAkira Matsuzawa, Masaya Miyahara. ieiceee, 15(5), 2018. [doi]
- An 84 dB dynamic range 62.5-625 kHz bandwidth clock-scalable noise-shaping SAR ADC with open-loop integrator using dynamic amplifierMasaya Miyahara, Akira Matsuzawa. cicc 2017: 1-4 [doi]
- Design of Interpolated Pipeline ADC Using Low-Gain Open-Loop AmplifiersHyunui Lee, Masaya Miyahara, Akira Matsuzawa. ieicet, 96-C(6):838-849, 2013. [doi]
- A 9-bit 1.8-GS/s pipelined ADC using linearized open-loop amplifiersLilan Yu, Masaya Miyahara, Akira Matsuzawa. asscc 2015: 1-4 [doi]