Area-delay efficient architecture for MP algorithm using reconfigurable inner-product circuits - researchr publication authors

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Pramod Kumar Meher, Basant K. Mohanty, Thambipillai Srikanthan. Area-delay efficient architecture for MP algorithm using reconfigurable inner-product circuits. In IEEE International Symposium on Circuits and Systemss, ISCAS 2014, Melbourne, Victoria, Australia, June 1-5, 2014. pages 2628-2631, IEEE, 2014. [doi]

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