Area-delay efficient architecture for MP algorithm using reconfigurable inner-product circuits

Pramod Kumar Meher, Basant K. Mohanty, Thambipillai Srikanthan. Area-delay efficient architecture for MP algorithm using reconfigurable inner-product circuits. In IEEE International Symposium on Circuits and Systemss, ISCAS 2014, Melbourne, Victoria, Australia, June 1-5, 2014. pages 2628-2631, IEEE, 2014. [doi]

@inproceedings{MeherMS14,
  title = {Area-delay efficient architecture for MP algorithm using reconfigurable inner-product circuits},
  author = {Pramod Kumar Meher and Basant K. Mohanty and Thambipillai Srikanthan},
  year = {2014},
  doi = {10.1109/ISCAS.2014.6865712},
  url = {http://dx.doi.org/10.1109/ISCAS.2014.6865712},
  researchr = {https://researchr.org/publication/MeherMS14},
  cites = {0},
  citedby = {0},
  pages = {2628-2631},
  booktitle = {IEEE International Symposium on Circuits and Systemss, ISCAS 2014, Melbourne, Victoria, Australia, June 1-5, 2014},
  publisher = {IEEE},
}