Design and failure analysis of logic-compatible multilevel gain-cell-based dram for fault-tolerant VLSI systems - researchr publication authors

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Pascal Andreas Meinerzhagen, Onur Andiç, Jürg Treichler, Andreas Peter Burg. Design and failure analysis of logic-compatible multilevel gain-cell-based dram for fault-tolerant VLSI systems. In David Atienza, Yuan Xie, José L. Ayala, Ken S. Stevens, editors, Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, Lausanne, Switzerland, May 2-6, 2011. pages 343-346, ACM, 2011. [doi]

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