A 1.8-GS/s 6-Bit Two-Step SAR ADC in 65-nm CMOS

Xiangyu Meng, Weihao Kong, Haifeng Yang, Yecong Li, Xuan Li. A 1.8-GS/s 6-Bit Two-Step SAR ADC in 65-nm CMOS. In IEEE International Symposium on Circuits and Systems, ISCAS 2021, Daegu, South Korea, May 22-28, 2021. pages 1-4, IEEE, 2021. [doi]

@inproceedings{MengKYLL21,
  title = {A 1.8-GS/s 6-Bit Two-Step SAR ADC in 65-nm CMOS},
  author = {Xiangyu Meng and Weihao Kong and Haifeng Yang and Yecong Li and Xuan Li},
  year = {2021},
  doi = {10.1109/ISCAS51556.2021.9401495},
  url = {https://doi.org/10.1109/ISCAS51556.2021.9401495},
  researchr = {https://researchr.org/publication/MengKYLL21},
  cites = {0},
  citedby = {0},
  pages = {1-4},
  booktitle = {IEEE International Symposium on Circuits and Systems, ISCAS 2021, Daegu, South Korea, May 22-28, 2021},
  publisher = {IEEE},
  isbn = {978-1-7281-9201-7},
}