A 4.2 mW 50 MS/s 13 bit CMOS SAR ADC With SNR and SFDR Enhancement Techniques

Takuji Miki, Takashi Morie, Kazuo Matsukawa, Yoji Bando, Takeshi Okumoto, Koji Obata, Shiro Sakiyama, Shiro Dosho. A 4.2 mW 50 MS/s 13 bit CMOS SAR ADC With SNR and SFDR Enhancement Techniques. J. Solid-State Circuits, 50(6):1372-1381, 2015. [doi]

@article{MikiMMBOOSD15,
  title = {A 4.2 mW 50 MS/s 13 bit CMOS SAR ADC With SNR and SFDR Enhancement Techniques},
  author = {Takuji Miki and Takashi Morie and Kazuo Matsukawa and Yoji Bando and Takeshi Okumoto and Koji Obata and Shiro Sakiyama and Shiro Dosho},
  year = {2015},
  doi = {10.1109/JSSC.2015.2417803},
  url = {http://dx.doi.org/10.1109/JSSC.2015.2417803},
  researchr = {https://researchr.org/publication/MikiMMBOOSD15},
  cites = {0},
  citedby = {0},
  journal = {J. Solid-State Circuits},
  volume = {50},
  number = {6},
  pages = {1372-1381},
}