Laurent Millet, Stéphane Chevobbe, Caaliph Andriamisaina, Edith Beigné, Fabrice Guellec, Thomas Dombek, L. Benaissa, E. Deschaseaux, M. Duranton, K. Benchehida, Mehdi Darouich, Maria Lepecq. A 5500FPS 85GOPS/W 3D Stacked BSI Vision Chip Based on Parallel in-Focal-Plane Acquisition and Processing. In 2018 IEEE Symposium on VLSI Circuits, Honolulu, HI, USA, June 18-22, 2018. pages 245-246, IEEE, 2018. [doi]
@inproceedings{MilletCABGDBDDB18,
title = {A 5500FPS 85GOPS/W 3D Stacked BSI Vision Chip Based on Parallel in-Focal-Plane Acquisition and Processing},
author = {Laurent Millet and Stéphane Chevobbe and Caaliph Andriamisaina and Edith Beigné and Fabrice Guellec and Thomas Dombek and L. Benaissa and E. Deschaseaux and M. Duranton and K. Benchehida and Mehdi Darouich and Maria Lepecq},
year = {2018},
doi = {10.1109/VLSIC.2018.8502290},
url = {https://doi.org/10.1109/VLSIC.2018.8502290},
researchr = {https://researchr.org/publication/MilletCABGDBDDB18},
cites = {0},
citedby = {0},
pages = {245-246},
booktitle = {2018 IEEE Symposium on VLSI Circuits, Honolulu, HI, USA, June 18-22, 2018},
publisher = {IEEE},
isbn = {978-1-5386-4214-6},
}