High speed stress tolerant 1.6 V - 3.6 V low to high voltage CMOS level shift architecture in 40 nm - researchr publication

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Sushrant Monga. High speed stress tolerant 1.6 V - 3.6 V low to high voltage CMOS level shift architecture in 40 nm. In 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012, Seoul, Korea (South), May 20-23, 2012. pages 2171-2174, IEEE, 2012. [doi]

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