2 4Gb DDR3 SDRAM with hybrid-I/O sense amplifier and segmented sub-array architecture - researchr publication authors

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Yongsam Moon, Yong-Ho Cho, Hyun Bae Lee, Byung-Hoon Jeong, Seok-Hun Hyun, Byungchul Kim, In-Chul Jeong, Seong-Young Seo, Junho Shin, Seok-Woo Choi, Ho-Sung Song, Jung Hwan Choi, Kyehyun Kyung, Young-Hyun Jun, Kinam Kim. 2 4Gb DDR3 SDRAM with hybrid-I/O sense amplifier and segmented sub-array architecture. In IEEE International Solid-State Circuits Conference, ISSCC 2009, Digest of Technical Papers, San Francisco, CA, USA, 8-12 February, 2009. pages 128-129, IEEE, 2009. [doi]

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