Yongsam Moon, Yong-Ho Cho, Hyun Bae Lee, Byung-Hoon Jeong, Seok-Hun Hyun, Byungchul Kim, In-Chul Jeong, Seong-Young Seo, Junho Shin, Seok-Woo Choi, Ho-Sung Song, Jung Hwan Choi, Kyehyun Kyung, Young-Hyun Jun, Kinam Kim. 2 4Gb DDR3 SDRAM with hybrid-I/O sense amplifier and segmented sub-array architecture. In IEEE International Solid-State Circuits Conference, ISSCC 2009, Digest of Technical Papers, San Francisco, CA, USA, 8-12 February, 2009. pages 128-129, IEEE, 2009. [doi]
@inproceedings{MoonCLJHKJSSCSCKJK09,
title = {2 4Gb DDR3 SDRAM with hybrid-I/O sense amplifier and segmented sub-array architecture},
author = {Yongsam Moon and Yong-Ho Cho and Hyun Bae Lee and Byung-Hoon Jeong and Seok-Hun Hyun and Byungchul Kim and In-Chul Jeong and Seong-Young Seo and Junho Shin and Seok-Woo Choi and Ho-Sung Song and Jung Hwan Choi and Kyehyun Kyung and Young-Hyun Jun and Kinam Kim},
year = {2009},
doi = {10.1109/ISSCC.2009.4977341},
url = {http://dx.doi.org/10.1109/ISSCC.2009.4977341},
researchr = {https://researchr.org/publication/MoonCLJHKJSSCSCKJK09},
cites = {0},
citedby = {0},
pages = {128-129},
booktitle = {IEEE International Solid-State Circuits Conference, ISSCC 2009, Digest of Technical Papers, San Francisco, CA, USA, 8-12 February, 2009},
publisher = {IEEE},
isbn = {978-1-4244-3458-9},
}