Michael Moreinis, Arkadiy Morgenshtein, Israel A. Wagner, Avinoam Kolodny. Logic Gates as Repeaters (LGR) for Area-Efficient Timing Optimization. IEEE Trans. VLSI Syst., 14(11):1276-1281, 2006. [doi]
@article{MoreinisMWK06,
title = {Logic Gates as Repeaters (LGR) for Area-Efficient Timing Optimization},
author = {Michael Moreinis and Arkadiy Morgenshtein and Israel A. Wagner and Avinoam Kolodny},
year = {2006},
doi = {10.1109/TVLSI.2006.886400},
url = {http://dx.doi.org/10.1109/TVLSI.2006.886400},
tags = {optimization, logic},
researchr = {https://researchr.org/publication/MoreinisMWK06},
cites = {0},
citedby = {0},
journal = {IEEE Trans. VLSI Syst.},
volume = {14},
number = {11},
pages = {1276-1281},
}