Shinichi Moriwaki, Atsushi Kawasumi, Toshikazu Suzuki, Takayasu Sakurai, Shinji Miyano. 0.4V SRAM with bit line swing suppression charge share hierarchical bit line scheme. In Rakesh Patel, Tom Andre, Aurangzeb Khan, editors, 2011 IEEE Custom Integrated Circuits Conference, CICC 2011, San Jose, CA, USA, Sept. 19-21, 2011. pages 1-4, IEEE, 2011. [doi]
@inproceedings{MoriwakiKSSM11,
title = {0.4V SRAM with bit line swing suppression charge share hierarchical bit line scheme},
author = {Shinichi Moriwaki and Atsushi Kawasumi and Toshikazu Suzuki and Takayasu Sakurai and Shinji Miyano},
year = {2011},
doi = {10.1109/CICC.2011.6055398},
url = {http://dx.doi.org/10.1109/CICC.2011.6055398},
researchr = {https://researchr.org/publication/MoriwakiKSSM11},
cites = {0},
citedby = {0},
pages = {1-4},
booktitle = {2011 IEEE Custom Integrated Circuits Conference, CICC 2011, San Jose, CA, USA, Sept. 19-21, 2011},
editor = {Rakesh Patel and Tom Andre and Aurangzeb Khan},
publisher = {IEEE},
isbn = {978-1-4577-0222-8},
}