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Marzieh Morshedzadeh, Ali Jahanian, Payam Pourashraf. Three-dimensional switchbox multiplexing in emerging 3D-FPGAs to reduce chip footprint and improve TSV usage. Integration, 50:81-90, 2015. [doi]
Possibly Related PublicationsThe following publications are possibly variants of this publication: Multiplexed switch box architecture in three-dimensional FPGAs to reduce silicon area and improve TSV usageMarzieh Morshedzadeh Morshedzadeh, Ali Jahanian. glvlsi 2012: 303-306 [doi] Three-Dimensional Physical Design Flow for Monolithic 3D-FPGAs to Improve Timing Closure and Chip AreaArmin Belghadr, Ali Jahanian. jcsc, 26(10):1-25, 2017. [doi] Improved timing closure by analytical buffer and TSV planning in three-dimensional chipsReza Abdollahi, Ali Jahanian. ieiceee, 9(24):1849-1854, 2012. [doi]
The following publications are possibly variants of this publication: