Simultaneous Placement and Buffer Planning for Reduction of Power Consumption in Interconnects and Repeaters - researchr publication authors

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Tudor Murgan, O. Mitrea, Sujan Pandey, Petru Bogdan Bacinschi, Manfred Glesner. Simultaneous Placement and Buffer Planning for Reduction of Power Consumption in Interconnects and Repeaters. In IFIP VLSI-SoC 2006, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Nice, France, 16-18 October 2006. pages 302-307, IEEE, 2006. [doi]

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