Tudor Murgan, O. Mitrea, Sujan Pandey, Petru Bogdan Bacinschi, Manfred Glesner. Simultaneous Placement and Buffer Planning for Reduction of Power Consumption in Interconnects and Repeaters. In IFIP VLSI-SoC 2006, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Nice, France, 16-18 October 2006. pages 302-307, IEEE, 2006. [doi]
@inproceedings{MurganMPBG06, title = {Simultaneous Placement and Buffer Planning for Reduction of Power Consumption in Interconnects and Repeaters}, author = {Tudor Murgan and O. Mitrea and Sujan Pandey and Petru Bogdan Bacinschi and Manfred Glesner}, year = {2006}, doi = {10.1109/VLSISOC.2006.313251}, url = {http://dx.doi.org/10.1109/VLSISOC.2006.313251}, tags = {power consumption}, researchr = {https://researchr.org/publication/MurganMPBG06}, cites = {0}, citedby = {0}, pages = {302-307}, booktitle = {IFIP VLSI-SoC 2006, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Nice, France, 16-18 October 2006}, publisher = {IEEE}, }