Clock Data Compensation Aware Digital Circuits Design for Voltage Margin Reduction

Taesik Na, Jong Hwan Ko, Saibal Mukhopadhyay. Clock Data Compensation Aware Digital Circuits Design for Voltage Margin Reduction. IEEE Trans. on Circuits and Systems, 64-I(9):2401-2413, 2017. [doi]

Authors

Taesik Na

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Jong Hwan Ko

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Saibal Mukhopadhyay

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