Taesik Na, Jong Hwan Ko, Saibal Mukhopadhyay. Clock Data Compensation Aware Digital Circuits Design for Voltage Margin Reduction. IEEE Trans. on Circuits and Systems, 64-I(9):2401-2413, 2017. [doi]
@article{NaKM17-0,
title = {Clock Data Compensation Aware Digital Circuits Design for Voltage Margin Reduction},
author = {Taesik Na and Jong Hwan Ko and Saibal Mukhopadhyay},
year = {2017},
doi = {10.1109/TCSI.2017.2695478},
url = {https://doi.org/10.1109/TCSI.2017.2695478},
researchr = {https://researchr.org/publication/NaKM17-0},
cites = {0},
citedby = {0},
journal = {IEEE Trans. on Circuits and Systems},
volume = {64-I},
number = {9},
pages = {2401-2413},
}