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A 40GOPS 250mW massively parallel processor based on matrix architecture

Masami Nakajima, Hideyuki Noda, Katsumi Dosaka, Kiyoshi Nakata, Motoki Higashida, Osamu Yamamoto, Katsuya Mizumoto, Hiroyuki Kondo, Yukihiko Shimazu, Kazutami Arimoto, Kazunori Saitoh, Toru Shimizu. A 40GOPS 250mW massively parallel processor based on matrix architecture. In 2006 IEEE International Solid State Circuits Conference, ISSCC 2006, Digest of Technical Papers, an Francisco, CA, USA, February 6-9, 2006. pages 1616-1625, IEEE, 2006. [doi]

Authors

Masami Nakajima

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Hideyuki Noda

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Katsumi Dosaka

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Kiyoshi Nakata

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Motoki Higashida

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Osamu Yamamoto

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Katsuya Mizumoto

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Hiroyuki Kondo

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Yukihiko Shimazu

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Kazutami Arimoto

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Kazunori Saitoh

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Toru Shimizu

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