The following publications are possibly variants of this publication:
- Low power design of a word-level finite field multiplier using Reordered Normal BasisParham Hosseinzadeh Namin, Roberto Muscedere, Majid Ahmadi. acssc 2015: 437-440 [doi]
- High-speed hardware implementation of a serial-in parallel-out finite field multiplier using reordered normal basisAshkan Hosseinzadeh Namin, Karl Leboeuf, Roberto Muscedere, Huapeng Wu, Majid Ahmadi. iet-cds, 4(2):168-179, 2010. [doi]
- A Word-Level Finite Field Multiplier Using Normal BasisAshkan Hosseinzadeh Namin, Huapeng Wu, Majid Ahmadi. TC, 60(6):890-895, 2011. [doi]
- Efficient VLSI Implementation of a Sequential Finite Field Multiplier Using Reordered Normal Basis in Domino LogicParham Hosseinzadeh Namin, Crystal Roma, Roberto Muscedere, Majid Ahmadi. tvlsi, 26(11):2542-2552, 2018. [doi]
- A High-Speed Word Level Finite Field Multiplier in BBF::2:::m::::: Using Redundant RepresentationAshkan Hosseinzadeh Namin, Huapeng Wu, Majid Ahmadi. tvlsi, 17(10):1546-1550, 2009. [doi]
- High-Speed Architectures for Multiplication Using Reordered Normal BasisAshkan Hosseinzadeh Namin, Huapeng Wu, Majid Ahmadi. TC, 61(2):164-172, 2012. [doi]
- High speed VLSI implementation of a finite field multiplier using redundant representationAshkan Hosseinzadeh Namin, Karl Leboeuf, Roberto Muscedere, Huapeng Wu, Majid Ahmadi. ecctd 2009: 161-164 [doi]