Nguyen T. H. Nguyen, Ediz Cetin, Oliver Diessel. Scheduling voter checks to detect configuration memory errors in FPGA-based TMR systems. In IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2017, Cambridge, United Kingdom, October 23-25, 2017. pages 1-4, IEEE, 2017. [doi]
@inproceedings{NguyenCD17-0, title = {Scheduling voter checks to detect configuration memory errors in FPGA-based TMR systems}, author = {Nguyen T. H. Nguyen and Ediz Cetin and Oliver Diessel}, year = {2017}, doi = {10.1109/DFT.2017.8244455}, url = {http://doi.ieeecomputersociety.org/10.1109/DFT.2017.8244455}, researchr = {https://researchr.org/publication/NguyenCD17-0}, cites = {0}, citedby = {0}, pages = {1-4}, booktitle = {IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2017, Cambridge, United Kingdom, October 23-25, 2017}, publisher = {IEEE}, isbn = {978-1-5386-0362-8}, }