Nguyen T. H. Nguyen, Ediz Cetin, Oliver Diessel. Scheduling voter checks to detect configuration memory errors in FPGA-based TMR systems. In IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2017, Cambridge, United Kingdom, October 23-25, 2017. pages 1-4, IEEE, 2017. [doi]
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