A novel memory cell for multiport RAM on 0.5 /spl mu/m CMOS Sea-of-Gates - researchr publication authors

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Koji Nii, Hideshi Maeno, Tokuya Osawa, Shuhei Iwade, Shinpei Kayano, Hiroshi Shibata. A novel memory cell for multiport RAM on 0.5 /spl mu/m CMOS Sea-of-Gates. J. Solid-State Circuits, 30(3):316-320, March 1995. [doi]

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