Koji Nii, Hideshi Maeno, Tokuya Osawa, Shuhei Iwade, Shinpei Kayano, Hiroshi Shibata. A novel memory cell for multiport RAM on 0.5 /spl mu/m CMOS Sea-of-Gates. J. Solid-State Circuits, 30(3):316-320, March 1995. [doi]
@article{NiiMOIKS95,
title = {A novel memory cell for multiport RAM on 0.5 /spl mu/m CMOS Sea-of-Gates},
author = {Koji Nii and Hideshi Maeno and Tokuya Osawa and Shuhei Iwade and Shinpei Kayano and Hiroshi Shibata},
year = {1995},
month = {March},
doi = {10.1109/4.364448},
url = {https://doi.org/10.1109/4.364448},
researchr = {https://researchr.org/publication/NiiMOIKS95},
cites = {0},
citedby = {0},
journal = {J. Solid-State Circuits},
volume = {30},
number = {3},
pages = {316-320},
}