Analysis and Techniques for Mitigating Interference From Power/Signal Lines and to SRAM Circuits in CMOS Inductive-Coupling Link for Low-Power 3-D System Integration - researchr publication authors

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Kiichi Niitsu, Yasufumi Sugimori, Yoshinori Kohama, Kenichi Osada, Naohiko Irie, Hiroki Ishikuro, Tadahiro Kuroda. Analysis and Techniques for Mitigating Interference From Power/Signal Lines and to SRAM Circuits in CMOS Inductive-Coupling Link for Low-Power 3-D System Integration. IEEE Trans. VLSI Syst., 19(10):1902-1907, 2011. [doi]

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