Kiichi Niitsu, Yasufumi Sugimori, Yoshinori Kohama, Kenichi Osada, Naohiko Irie, Hiroki Ishikuro, Tadahiro Kuroda. Analysis and Techniques for Mitigating Interference From Power/Signal Lines and to SRAM Circuits in CMOS Inductive-Coupling Link for Low-Power 3-D System Integration. IEEE Trans. VLSI Syst., 19(10):1902-1907, 2011. [doi]
@article{NiitsuSKOIIK11,
title = {Analysis and Techniques for Mitigating Interference From Power/Signal Lines and to SRAM Circuits in CMOS Inductive-Coupling Link for Low-Power 3-D System Integration},
author = {Kiichi Niitsu and Yasufumi Sugimori and Yoshinori Kohama and Kenichi Osada and Naohiko Irie and Hiroki Ishikuro and Tadahiro Kuroda},
year = {2011},
doi = {10.1109/TVLSI.2010.2056711},
url = {http://dx.doi.org/10.1109/TVLSI.2010.2056711},
tags = {analysis},
researchr = {https://researchr.org/publication/NiitsuSKOIIK11},
cites = {0},
citedby = {0},
journal = {IEEE Trans. VLSI Syst.},
volume = {19},
number = {10},
pages = {1902-1907},
}