Low-Power, Energy-Efficient Full Adder for Deep-Submicron Design

Mallikarjuna Rao Nimmagadda, Ajit Pal. Low-Power, Energy-Efficient Full Adder for Deep-Submicron Design. In IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011, 4-6 July 2011, Chennai, India. pages 345-346, IEEE Computer Society, 2011. [doi]

@inproceedings{NimmagaddaP11,
  title = {Low-Power, Energy-Efficient Full Adder for Deep-Submicron Design},
  author = {Mallikarjuna Rao Nimmagadda and Ajit Pal},
  year = {2011},
  doi = {10.1109/ISVLSI.2011.28},
  url = {http://dx.doi.org/10.1109/ISVLSI.2011.28},
  tags = {design},
  researchr = {https://researchr.org/publication/NimmagaddaP11},
  cites = {0},
  citedby = {0},
  pages = {345-346},
  booktitle = {IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2011, 4-6 July 2011, Chennai, India},
  publisher = {IEEE Computer Society},
}