Hideyuki Nosaka, Eiichi Sano, Kiyoshi Ishii, Minoru Ida, Kenji Kurishima, Shoji Yamahata, Tsugumichi Shibata, Hiroyuki Fukuyama, Mikio Yoneyama, Takatomo Enoki, Masahiro Muraguchi. A 39-to-45-Gbit/s multi-data-rate clock and data recovery circuit with a robust lock detector. J. Solid-State Circuits, 39(8):1361-1365, 2004. [doi]
Abstract is missing.