Takatomo Enoki - researchr alias

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Viewing Publication 1 - 16 from 16

2009

2006

Special Section on Heterostructure Microelectronics with TWHM2005Takatomo Enoki. ieicet, 89-C(7):873, 2006. [doi]

W-Band Active Integrated Antenna Oscillator Based on Full-Wave Design Methodology and 0.1-µm Gate InP-Based HEMTsKoji Inafune, Eiichi Sano, Hideaki Matsuzaki, Toshihiko Kosugi, Takatomo Enoki. ieicet, 89-C(7):954-958, 2006. [doi]

Novel Fabrication Technology for High Yield Sub-100-nm-Gate InP-Based HEMTsHideaki Matsuzaki, Takashi Maruyama, Takatomo Enoki, Masami Tokumitsu. ieicet, 89-C(7):949-953, 2006. [doi]

2005

High-bit-rate low-power decision circuit using InP-InGaAs HBT technologyKiyoshi Ishii, Hideyuki Nosaka, Kimikazu Sano, Koichi Murata, Minoru Ida, Kenji Kurishima, Michihiro Hirata, Tsugumichi Shibata, Takatomo Enoki. jssc, 40(7):1583-1588, 2005. [doi]

2004

Photoreceiver module using an InP HEMT transimpedance amplifier for over 40 gb/sHiroyuki Fukuyama, Kimikazu Sano, Koichi Murata, Hiroto Kitabayashi, Yasuro Yamane, Takatomo Enoki, Hirohiko Sugahara. jssc, 39(10):1690-1696, 2004. [doi]

Low-power and High-speed SCFL-inverter Using Pseudomorphic InGaAs Channel High Electron Mobility TransistorsHideaki Matsuzaki, Kimikazu Sano, Takatomo Enoki. ieiceee, 1(2):24-28, 2004. [doi]

Suppression of short-channel effect in pseudomorphic In0.25Al0.75P/In0.75Ga0.25As high electron mobility transistorsHideaki Matsuzaki, Hiroki Sugiyama, Haruki Yokoyama, Takashi Kobayashi, Takatomo Enoki. ieiceee, 1(11):292-297, 2004. [doi]

100-Gb/s multiplexing and demultiplexing IC operations in InP HEMT technologyKoichi Murata, Kimikazu Sano, Hiroto Kitabayashi, Suehiro Sugitani, Hirohiko Sugahara, Takatomo Enoki. jssc, 39(1):207-213, 2004. [doi]

A 39-to-45-Gbit/s multi-data-rate clock and data recovery circuit with a robust lock detectorHideyuki Nosaka, Eiichi Sano, Kiyoshi Ishii, Minoru Ida, Kenji Kurishima, Shoji Yamahata, Tsugumichi Shibata, Hiroyuki Fukuyama, Mikio Yoneyama, Takatomo Enoki, Masahiro Muraguchi. jssc, 39(8):1361-1365, 2004. [doi]

2003

A 10-Gb/s data-pattern independent clock and data recovery circuit with a two-mode phase comparatorHideyuki Nosaka, Kiyoshi Ishii, Takatomo Enoki, Tsugumichi Shibata. jssc, 38(2):192-197, 2003. [doi]

50-Gb/s 4-b multiplexer/demultiplexer chip set using InP HEMTsKimikazu Sano, Koichi Murata, Suehiro Sugitani, Hirohiko Sugahara, Takatomo Enoki. jssc, 38(9):1504-1511, 2003. [doi]

2002

Low-power 1: 16 DEMUX and one-chip CDR with 1: 4 DEMUX using InP-InGaAs heterojunction bipolar transistorsKiyoshi Ishii, Hideyuki Nosaka, Hiroki Nakajima, Kenji Kurishima, Minoru Ida, Noriyuki Watanabe, Yasurou Yamane, Eiichi Sano, Takatomo Enoki. jssc, 37(9):1146-1151, 2002. [doi]

1998

An 80-Gbit/s multiplexer IC using InAlAs/InGaAs/InP HEMTsTaiichi Otsuji, Koichi Murata, Takatomo Enoki, Yohtaro Umeda. jssc, 33(9):1321-1327, 1998. [doi]

1997

40-Gb/s ICs for future lightwave communications systemsTaiichi Otsuji, Yuhki Imai, Eiichi Sano, Shunji Kimura, Satoshi Yamaguchi, Mikio Yoneyama, Takatomo Enoki, Yohtaro Umeda. jssc, 32(9):1363-1370, 1997. [doi]

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