Fully integrated CMOS phase-locked loop with 15 to 240 MHz locking range and /spl plusmn/50 ps jitter - researchr publication authors

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Ilya I. Novof, John Austin, Ram Kelkar, Don Strayer, Steve Wyatt. Fully integrated CMOS phase-locked loop with 15 to 240 MHz locking range and /spl plusmn/50 ps jitter. J. Solid-State Circuits, 30(11):1259-1266, November 1995. [doi]

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