Fully integrated CMOS phase-locked loop with 15 to 240 MHz locking range and /spl plusmn/50 ps jitter

Ilya I. Novof, John Austin, Ram Kelkar, Don Strayer, Steve Wyatt. Fully integrated CMOS phase-locked loop with 15 to 240 MHz locking range and /spl plusmn/50 ps jitter. J. Solid-State Circuits, 30(11):1259-1266, November 1995. [doi]

@article{NovofAKSW95,
  title = {Fully integrated CMOS phase-locked loop with 15 to 240 MHz locking range and /spl plusmn/50 ps jitter},
  author = {Ilya I. Novof and John Austin and Ram Kelkar and Don Strayer and Steve Wyatt},
  year = {1995},
  month = {November},
  doi = {10.1109/4.475714},
  url = {https://doi.org/10.1109/4.475714},
  researchr = {https://researchr.org/publication/NovofAKSW95},
  cites = {0},
  citedby = {0},
  journal = {J. Solid-State Circuits},
  volume = {30},
  number = {11},
  pages = {1259-1266},
}