Leveraging Gate-Level Properties to Identify Hardware Timing Channels

Jason Oberg, Sarah Meiklejohn, Timothy Sherwood, Ryan Kastner. Leveraging Gate-Level Properties to Identify Hardware Timing Channels. IEEE Trans. on CAD of Integrated Circuits and Systems, 33(9):1288-1301, 2014. [doi]

Authors

Jason Oberg

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Sarah Meiklejohn

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Timothy Sherwood

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Ryan Kastner

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