Jason Oberg, Sarah Meiklejohn, Timothy Sherwood, Ryan Kastner. Leveraging Gate-Level Properties to Identify Hardware Timing Channels. IEEE Trans. on CAD of Integrated Circuits and Systems, 33(9):1288-1301, 2014. [doi]
@article{ObergMSK14,
title = {Leveraging Gate-Level Properties to Identify Hardware Timing Channels},
author = {Jason Oberg and Sarah Meiklejohn and Timothy Sherwood and Ryan Kastner},
year = {2014},
doi = {10.1109/TCAD.2014.2331332},
url = {http://dx.doi.org/10.1109/TCAD.2014.2331332},
researchr = {https://researchr.org/publication/ObergMSK14},
cites = {0},
citedby = {0},
journal = {IEEE Trans. on CAD of Integrated Circuits and Systems},
volume = {33},
number = {9},
pages = {1288-1301},
}