Gotaro Odawara, Takahisa Hiraide, Osamu Nishina. Partitioning and Placement Technique for CMOS Gate Arrays. IEEE Trans. on CAD of Integrated Circuits and Systems, 6(3):355-363, 1987. [doi]
@article{OdawaraHN87, title = {Partitioning and Placement Technique for CMOS Gate Arrays}, author = {Gotaro Odawara and Takahisa Hiraide and Osamu Nishina}, year = {1987}, url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=28441&arnumber=1270280&count=21&index=5}, tags = {partitioning}, researchr = {https://researchr.org/publication/OdawaraHN87}, cites = {0}, citedby = {0}, journal = {IEEE Trans. on CAD of Integrated Circuits and Systems}, volume = {6}, number = {3}, pages = {355-363}, }