A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction

Tae-young Oh, Young-Soo Sohn, Seung-Jun Bae, Min-Sang Park, Ji-Hoon Lim, Yong-Ki Cho, Dae-Hyun Kim, Dong-Min Kim, Hye-Ran Kim, Hyun Joong Kim, Jin Hyun Kim, Jin Kook Kim, Young-Sik Kim, Byeong-Cheol Kim, Sang-Hyup Kwak, Jae-Hyung Lee, Jae Young Lee, Chang-Ho Shin, Yun-Seok Yang, Beom-Sig Cho, Sam-Young Bang, Hyang-Ja Yang, Young-Ryeol Choi, Gil-Shin Moon, Cheol-Goo Park, Seokwon Hwang, Jeong-Don Lim, Kwang-Il Park, Joo-Sun Choi, Young-Hyun Jun. A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction. J. Solid-State Circuits, 46(1):107-118, 2011. [doi]

Abstract

Abstract is missing.