A 12.5-Gb/s Parallel Phase Detection Clock and Data Recovery Circuit in 0.13-$muhbox m$CMOS

Yusuke Ohtomo, Kazuyoshi Nishimura, Masafumi Nogawa. A 12.5-Gb/s Parallel Phase Detection Clock and Data Recovery Circuit in 0.13-$muhbox m$CMOS. J. Solid-State Circuits, 41(9):2052-2057, 2006. [doi]

Authors

Yusuke Ohtomo

This author has not been identified. Look up 'Yusuke Ohtomo' in Google

Kazuyoshi Nishimura

This author has not been identified. Look up 'Kazuyoshi Nishimura' in Google

Masafumi Nogawa

This author has not been identified. Look up 'Masafumi Nogawa' in Google