Yusuke Ohtomo, Kazuyoshi Nishimura, Masafumi Nogawa. A 12.5-Gb/s Parallel Phase Detection Clock and Data Recovery Circuit in 0.13-$muhbox m$CMOS. J. Solid-State Circuits, 41(9):2052-2057, 2006. [doi]
@article{OhtomoNN06,
title = {A 12.5-Gb/s Parallel Phase Detection Clock and Data Recovery Circuit in 0.13-$muhbox m$CMOS},
author = {Yusuke Ohtomo and Kazuyoshi Nishimura and Masafumi Nogawa},
year = {2006},
doi = {10.1109/JSSC.2006.880617},
url = {https://doi.org/10.1109/JSSC.2006.880617},
researchr = {https://researchr.org/publication/OhtomoNN06},
cites = {0},
citedby = {0},
journal = {J. Solid-State Circuits},
volume = {41},
number = {9},
pages = {2052-2057},
}