Y. Okamoto, Y. Komura, T. Mizuguchi, T. Saito, M. Ito, K. Kimura, Tatsuya Onuki, Yoshinori Ando, H. Sawai, T. Murakawa, H. Kunitake, Takanori Matsuzaki, H. Kimura, M. Fujita, M. Ikeda, Shunpei Yamazaki. 1Mbit 1T1C 3D DRAM with Monolithically Stacked One Planar FET and Two Vertical FET Heterogeneous Oxide Semiconductor layers over Si CMOS. In 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Kyoto, Japan, June 11-16, 2023. pages 1-2, IEEE, 2023. [doi]
Abstract is missing.