A design methodology for SAR ADC optimal redundancy bit

Toru Okazaki, Daisuke Kanemoto, Ramesh K. Pokharel, Keiji Yoshida, Haruichi Kanaya. A design methodology for SAR ADC optimal redundancy bit. IEICE Electronic Express, 11(10):20140218, 2014. [doi]

Authors

Toru Okazaki

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Daisuke Kanemoto

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Ramesh K. Pokharel

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Keiji Yoshida

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Haruichi Kanaya

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