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Double Patterning Lithography (DPL)-compliant layout construction (DCLC) with area-stitch usage tradeoff

Debasis Pal, Abir Pramanik, Parthasarathi Dasgupta, Debesh Kumar Das. Double Patterning Lithography (DPL)-compliant layout construction (DCLC) with area-stitch usage tradeoff. In 20th International Symposium on VLSI Design and Test, VDAT 2016, Guwahati, India, May 24-27, 2016. pages 1-6, IEEE, 2016. [doi]

Authors

Debasis Pal

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Abir Pramanik

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Parthasarathi Dasgupta

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Debesh Kumar Das

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