Debasis Pal, Abir Pramanik, Parthasarathi Dasgupta, Debesh Kumar Das. Double Patterning Lithography (DPL)-compliant layout construction (DCLC) with area-stitch usage tradeoff. In 20th International Symposium on VLSI Design and Test, VDAT 2016, Guwahati, India, May 24-27, 2016. pages 1-6, IEEE, 2016. [doi]
@inproceedings{PalPDD16, title = {Double Patterning Lithography (DPL)-compliant layout construction (DCLC) with area-stitch usage tradeoff}, author = {Debasis Pal and Abir Pramanik and Parthasarathi Dasgupta and Debesh Kumar Das}, year = {2016}, doi = {10.1109/ISVDAT.2016.8064875}, url = {https://doi.org/10.1109/ISVDAT.2016.8064875}, researchr = {https://researchr.org/publication/PalPDD16}, cites = {0}, citedby = {0}, pages = {1-6}, booktitle = {20th International Symposium on VLSI Design and Test, VDAT 2016, Guwahati, India, May 24-27, 2016}, publisher = {IEEE}, isbn = {978-1-5090-1422-4}, }