Subhankar Pal, Chetan Vudadha, Sai Phaneendra P., Sreehari Veeramachaneni, Srinivas Mandalika. A New Design of an N-Bit Reversible Arithmetic Logic Unit. In 2014 Fifth International Symposium on Electronic System Design, Surathkal, Mangalore, India, December 15-17, 2014. pages 224-225, IEEE, 2014. [doi]
@inproceedings{PalVPVM14,
title = {A New Design of an N-Bit Reversible Arithmetic Logic Unit},
author = {Subhankar Pal and Chetan Vudadha and Sai Phaneendra P. and Sreehari Veeramachaneni and Srinivas Mandalika},
year = {2014},
doi = {10.1109/ISED.2014.56},
url = {https://doi.org/10.1109/ISED.2014.56},
researchr = {https://researchr.org/publication/PalVPVM14},
cites = {0},
citedby = {0},
pages = {224-225},
booktitle = {2014 Fifth International Symposium on Electronic System Design, Surathkal, Mangalore, India, December 15-17, 2014},
publisher = {IEEE},
isbn = {978-1-4799-6965-4},
}