Subhankar Pal, Chetan Vudadha, Sai Phaneendra P., Sreehari Veeramachaneni, Srinivas Mandalika. A New Design of an N-Bit Reversible Arithmetic Logic Unit. In 2014 Fifth International Symposium on Electronic System Design, Surathkal, Mangalore, India, December 15-17, 2014. pages 224-225, IEEE, 2014. [doi]
Abstract is missing.