Ayan Palchaudhuri, Anindya Sundar Dhar. Speed-area optimized VLSI architecture of multi-bit cellular automaton cell based random number generator on FPGA with testable logic support. J. Parallel Distrib. Comput., 151:13-23, 2021. [doi]
@article{PalchaudhuriD21,
title = {Speed-area optimized VLSI architecture of multi-bit cellular automaton cell based random number generator on FPGA with testable logic support},
author = {Ayan Palchaudhuri and Anindya Sundar Dhar},
year = {2021},
doi = {10.1016/j.jpdc.2021.01.005},
url = {https://doi.org/10.1016/j.jpdc.2021.01.005},
researchr = {https://researchr.org/publication/PalchaudhuriD21},
cites = {0},
citedby = {0},
journal = {J. Parallel Distrib. Comput.},
volume = {151},
pages = {13-23},
}