Speed-area optimized VLSI architecture of multi-bit cellular automaton cell based random number generator on FPGA with testable logic support - researchr publication

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Ayan Palchaudhuri, Anindya Sundar Dhar. Speed-area optimized VLSI architecture of multi-bit cellular automaton cell based random number generator on FPGA with testable logic support. J. Parallel Distrib. Comput., 151:13-23, 2021. [doi]

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