Chet A. Palesko, Lex A. Akers. Logic Partitioning for Minimizing Gate Arrays. IEEE Trans. on CAD of Integrated Circuits and Systems, 2(2):117-121, 1983. [doi]
@article{PaleskoA83,
title = {Logic Partitioning for Minimizing Gate Arrays},
author = {Chet A. Palesko and Lex A. Akers},
year = {1983},
url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=28424&arnumber=1270028&count=9&index=7},
tags = {logic, partitioning},
researchr = {https://researchr.org/publication/PaleskoA83},
cites = {0},
citedby = {0},
journal = {IEEE Trans. on CAD of Integrated Circuits and Systems},
volume = {2},
number = {2},
pages = {117-121},
}