Timing Arc based logic analysis for false noise reduction

Murthy Palla, Jens Bargfrede, Stephan Eggersglüß, Walter Anheier, Rolf Drechsler. Timing Arc based logic analysis for false noise reduction. In 2009 International Conference on Computer-Aided Design (ICCAD 09), November 2-5, 2009, San Jose, CA, USA. pages 225-230, IEEE, 2009. [doi]

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