Yunbing Pang, Jiqing Xu, Zhiyin Lu, Zhengjie Li, Yufan Zhang, Jinmei Lai. Research on Area Modeling Methodology for FPGA Interconnect Circuits. In 13th IEEE International Conference on ASIC, ASICON 2019, Chongqing, China, October 29 - November 1, 2019. pages 1-4, IEEE, 2019. [doi]
@inproceedings{PangXLLZL19,
title = {Research on Area Modeling Methodology for FPGA Interconnect Circuits},
author = {Yunbing Pang and Jiqing Xu and Zhiyin Lu and Zhengjie Li and Yufan Zhang and Jinmei Lai},
year = {2019},
doi = {10.1109/ASICON47005.2019.8983580},
url = {https://doi.org/10.1109/ASICON47005.2019.8983580},
researchr = {https://researchr.org/publication/PangXLLZL19},
cites = {0},
citedby = {0},
pages = {1-4},
booktitle = {13th IEEE International Conference on ASIC, ASICON 2019, Chongqing, China, October 29 - November 1, 2019},
publisher = {IEEE},
isbn = {978-1-7281-0735-6},
}