Se-Jeong Park, Jeong-Su Kim, Ramchan Woo, Se-Joong Lee, Kang Min Lee, Tae-Hum Yang, Jin-Yong Jung, Hoi-Jun Yoo. A reconfigurable multilevel parallel texture cache memory with 75-GB/s parallel cache replacement bandwidth. J. Solid-State Circuits, 37(5):612-623, 2002. [doi]
@article{ParkKWLLYJY02,
title = {A reconfigurable multilevel parallel texture cache memory with 75-GB/s parallel cache replacement bandwidth},
author = {Se-Jeong Park and Jeong-Su Kim and Ramchan Woo and Se-Joong Lee and Kang Min Lee and Tae-Hum Yang and Jin-Yong Jung and Hoi-Jun Yoo},
year = {2002},
doi = {10.1109/4.997855},
url = {https://doi.org/10.1109/4.997855},
researchr = {https://researchr.org/publication/ParkKWLLYJY02},
cites = {0},
citedby = {0},
journal = {J. Solid-State Circuits},
volume = {37},
number = {5},
pages = {612-623},
}