Se-Jeong Park, Jeong-Su Kim, Ramchan Woo, Se-Joong Lee, Kang Min Lee, Tae-Hum Yang, Jin-Yong Jung, Hoi-Jun Yoo. A reconfigurable multilevel parallel texture cache memory with 75-GB/s parallel cache replacement bandwidth. J. Solid-State Circuits, 37(5):612-623, 2002. [doi]
Abstract is missing.